Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are commonly used in high-voltage applications because of their high breakdown voltage characteristics. The layout geometry of a typical LDMOS transistor includes curved regions such as when the transistor is formed in loops, or when the LDMOS transistor is shaped in an oval or racetrack-like configuration with rectilinear portions between the curved regions.
It is well known that the layout geometry of an LDMOS transistor can have an adverse impact on device characteristics, such as the breakdown voltage, of the transistor. Specifically, when the layout geometry of an LDMOS transistor includes curved regions, the LDMOS transistor can suffer from a low breakdown voltage at the curved regions due to electric field crowding effects. Electric field crowding effects describe the conditions where the surface electric field of an LDMOS transistor is higher at the curved regions of the transistor as compared to the parallel rectilinear regions due to electric field crowding at the curved regions. Thus, the breakdown voltage of the overall LDMOS transistor is limited by the breakdown voltage of the curved regions.
Approaches for reducing the electric field crowding at the curved regions of an LDMOS transistor by altering the dimensions and the relative dimensions of the respective transistor features, undesirably introduce variations to device performance and alter device characteristics and functionality of the transistors. In general, increasing the breakdown voltage typically involves a higher on-state resistance (RON). An increase in on-state resistance of a transistor is undesirable, especially for high-voltage applications.
Therefore, it would be desirable to optimize the breakdown voltage characteristics of an LDMOS transistor over the entire layout geometry of the transistor without adversely impacting other device characteristics of the transistor.